Silicon photonics based on CMOS processing technology will potentially enable the integration of optical devices with electronics on a single chip. Furthermore, the high-index difference between Si and SiO2 from the silicon-on-insulator (SOI) material system, together with suitable optical waveguide geometry, provides for strong-confinement waveguides with very low bending losses from a small bending radius. This allows for a very high density of optical devices and compact integrated functionally that could be inherently scalable for high-volume, low-cost production by utilizing highly mature fabrication and processing techniques developed for the VLSI microelectronics industry. However, one consequence of the high-index contrast and strong confinement optical waveguide system is the high propagation loss caused by surface or interface roughness introduced during the waveguide fabrication process by waveguide definition (photolithography, etching or other fabrication steps). The ability to fabricate very low-loss optical waveguides in silicon is an important step for silicon photonics to reach its full potential.
The currently used common fabrication techniques for producing silicon waveguides are reactive ion etching (RIE), and wet-chemical etching (both anisotropic and isotropic). Reactive-ion etching is used for achieving sub-micron features with high-resolution in the silicon processing industry. The process is anisotropic and can be used to produce rib and strip waveguides of the geometries described in more detail below in relation to FIGS. 1-3. The process produces vertical side walls, but will transfer any roughness in the preceding mask layer (introduced, say, from unintentional and often unavoidable variations in the photoresist side-walls during the photolithography step) and also introduce roughness inherent to the etching process itself. The surface roughness is typically on the 10 nm scale, and although this seems small, it is significant enough to cause propagation losses on the order of 2-20 dB/cm for strong-confinement strip waveguides. The impact on large-area rib waveguides is less severe. Using anisotropic wet-chemical silicon etchants such as potassium hydroxide (KOH) can in theory produce waveguide sidewalls that are atomically smooth. However, the sidewalls are no longer vertical, which has little impact on the waveguiding properties, but the sidewalls are limited to well-defined crystal directions. This limits the optical circuit geometry to straight waveguides only, which is of limited practical use. High-density optical circuits will require curves, S-bends, and waveguides at arbitrary angles. Finally, it is also possible to use an isotropic wet-chemical silicon etchant like the HNA etchant (hydrofluoric acid or ammonium fluoride, nitric acid, and acetic acid or water) for the optical waveguides. This etchant can produce relatively smooth surfaces but typically not as smooth as the original, unetched silicon wafer surface. Moreover, it is usually difficult to control the etching rate for precise rib height control using this process.
A recently proposed solution to the RIE induced surface roughness problem for the strip waveguide geometry is that of oxidation smoothing, described, for example, in Lee et al, “Fabrication of Ultralow-loss Si/SiO2 Waveguides by Roughness Reduction,” Optics Letters, vol. 26, pp 1888-1890 (December, 2001). There, the rough silicon surface is oxidized in an oxidizing environment, such as at a temperature of 1000 deg C. in an oxygen (O2 with/without H2O) atmosphere for an extended time of 30-60 min. The principle there relies on the result that the convex points in the rough surface react faster than the concave points, thus leading to an overall smoothing effect. (See also, U.S. Patent Publication 2002/0031321, published Mar. 14, 2002.) The resultant SiO2 layer formed on this surface can be etched away in HF. It has been shown that this process can reduce the root mean square (rms) surface roughness of an RIE silicon waveguide from σ=10 nm to about σ=2 mm. This results in a propagation loss for the strip waveguide being reduced from about 32 dB/cm after RIE formation to 0.8 dB/cm after oxidation smoothing. This process does not significantly affect the correlation length Lc of any rough surfaces which is also an important parameter in the propagation loss behavior of an optical waveguide. The correlation length, while a precise mathematical construct, can generally be understood to be the length over which a roughness feature extends along the waveguide length. It should be noted that in this technique, the waveguide is pre-existing and has been formed using some form of etching process as described above, and thus will start with some undesirable amount of surface roughness from that process.
Other proposals have been made regarding formation of optical waveguides using oxidation of silicon. For example, Pearson, et al “Fabrication of SiGe Optical Waveguides Using VLSI Processing Techniques,” Journal of Lightwave Technology, vol. 19, pp 363-370 (March 2001) suggests oxidation of a silicon cladding layer by wet oxidation. Pearson's technique is directed to waveguides with a SiGe core and Si cladding, which produces a small difference in index of refraction between the core and cladding. This, in turn, requires a large thickness of the core and cladding (at least 0.5 microns). To provide guiding in these large-dimension guides, Pearson et al use a process which oxidizes the cladding layers of the guide in a region removed from the core of the guide. It is understood by those skilled in the art that the waveguide core is a higher index medium where the electromagnetic field is propagating, while the cladding is a lower index medium where the electromagnetic field is evanescently decaying serving to confine the electromagnetic field in the core by total internal reflection. The incorporation of a SiGe core, and the corresponding larger waveguide sizes that must be used in the weakly-guided structures defined by patterning only the cladding, are not optimal for many integrated optoelectronic applications. Further, Pearson's technique is used to reduce dislocation density in the SiGe core, and does not address the smoothing or other properties of the core-cladding interface, which in their case is an epitaxially grown SiGe—Si interface. In a similar proposal, U.S. Pat. No. 5,917,981 issued to Kovacic et al, involves fabricating waveguides including the step of wet oxidation of a silicon cladding layer. Again, this proposal is directed to the low index of refraction difference structures (Δn˜0.05) with large thicknesses of silicon (typically about 1 micron). (See, e.g., column 7, lines 22-27 of the patent.)
Finally, U.S. Pat. No. 5,360,982 issued to Venhuizen discloses fabrication of a device with a groove-shaped waveguide, where the groove is formed with smooth surfaces by virtue of oxidation of a silicon substrate. This proposal is also directed to fairly large dimensions. For example, the groove depth varies from 0.1 to 1 micron. (See, e.g., col. 2 lines 44-49.) Further, the waveguide material is a polymer which is formed after the groove, thus requiring two steps for smoothing and waveguide formation.
It is, therefore, desirable to fabricate a waveguide device with a large difference in index of refraction between the core and cladding for tight optical confinement using a minimum number of steps while producing a smooth core-cladding interface to achieve a low loss.